This invention generally related to the manufacture of semiconductors, and more specifically relates to a design which allows burn-in of DRAM""s at the wafer level, as opposed to in die form or after the package has been assembled.
When manufacturing semiconductors (and related devices and systems), it is important to run the device under voltage and temperature stress conditions for a short period of time, usually 48 hours, to ensure that all components work properly, and continue to do so for a period of time. This testing process is called xe2x80x9cburn-inxe2x80x9d, and provides at least some assurance that the device will work in the field, at least for a period of time.
Some multi-chip modules or packages (MCM""s) include DRAM""s. All of the DRAM""s in an MCM must go through burn-in in order to weed out (i.e. discover) infant mortality. With existing processes, the DRAM""s have to be burnt-in either in die form or in the final assembled package with the other dice in the package. Without burning-in the DRAM""s, DPPM (Defective Parts Per Million) can be easily over 10,000.
Currently, the best alternative is to burn-in the DRAM""s in die form. However, this requires that special die packages be built, and this can be quite costly. In fact, the cost can be in the order of tens of millions of dollars.
While burning in the DRAM""s after the package has been assembled is a possibility, this is also costly due to the fact that the entire package has to be discarded if any of the DRAM""s in the package fails.
Neither burn-in method (i.e. burn-in when the DRAM is in die form, and burn-in after the package has been assembled) allows burn-in to be performed with simple wafer sort probing equipment.
A general object of an embodiment of the present invention is to provide a design which allows burn-in of DRAM""s at the wafer level, as opposed to in die form or after the package has been assembled.
Another object of an embodiment of the present invention is to provide a design which allows burn-in to be performed with simple wafer sort probing equipment.
Briefly, and in accordance with at least one of the foregoing objects, an embodiment of the present invention provides a DRAM wafer that includes a plurality of DRAM dies daisy chained together. The DRAM dies are daisy chained in that an output pad of one DRAM die is connected to the input pad of a next DRAM die on the wafer, etc., etc.
Preferably, the DRAM dies are IEE1149.1 (JTAG) compliant, and include the following pads: TDI (Test Data In), TDO (Test Data Out), TCK (Test Clock) and TMS (Test Mode Set). The TDO pad of each DRAM die is connected to the TDI pad of the next DRAM die on the wafer. Additionally, the TMS and TCK pads of the DRAM dies are connected in parallel, such as via metal lines running along the scribe area of the wafer.
Preferably, the DRAM dies on the wafer are arranged in rows, and each DRAM die in a given row is daisy chained to the next DRAM die in the row (i.e. the TDO pad of each DRAM die in the row is connected to the TDI pad of the next DRAM die in the row), and the last DRAM die in the row is daisy chained to the first DRAM die in the next row (i.e. the TDO pad of the last DRAM die in a given row is connected to the TDI pad of the first DRAM die in the next row). Preferably, the last DRAM die in a given row is daisy chained to the first DRAM die in the next row via a metal line on the scribe area of the wafer. The DRAM dies on the wafer are connected to power busses along the scribe area so that the individual dies can be powered.